The present invention relates to an analog/digital converter.
Analog/digital converters—frequently also called A/D converters—are electronic circuits which convert an analog input variable, for example an input voltage or an input current, into a proportional digital output variable, which are able to be output as a binary thermometer code encoded output signal, for example. Many kinds of A/D converter types are known for analog/digital conversion, for example parallel operation A/D converters (flash converters), cascade A/D converters (subranging converters), and A/D converters operating on the basis of the weighing process or the principle of successive approximation (in this regard see Tietze, Schenk, Halbleiterschaltungstechnik [Semiconductor circuitry], 10th edition, particularly pages 780 ff).
The process of successive approximation involves the data bits of a digital output variable being determined successively one after the other from an input variable in weighing steps. FIG. 4 shows the basic design of a successive approximation A/D converter 1 described, for example, in German patent DE 101 39 488 C1. The A/D converter 1 has a sample and hold circuit 2 (hold and track circuit) on its input for the purpose of sampling and storing an analog input signal UE. The sample and hold circuit 2 buffer-stores the input signal UE in order to ensure that changes in the input signal UE cause no errors during the conversion period. In addition, a comparator 3 is provided for comparing the stored analog input signal UE with the analog intermediate signal UZ derived from the digital output signal UD. The analog intermediate signal UZ is obtained by feeding back the digital output signal UD produced by an SAR register 4 (SAR=Successive Approximation Register) and subsequent digital/analog conversion. For this, an n-bit D/A converter 5 is provided, with n denoting the resolution of the D/A conversion in this case.
During the successive approximation, the most significant bit (MSB) is set first of all and then the digital/analog converter is used to ascertain the associated value of an analog voltage. If the input analog voltage UE to be converted is larger than the ascertained output analog voltage UZ from the digital/analog converter then the set bit remains set. In the opposite case, it is reset again. The next least significant bit is then determined in the same way. In this way, the process is continued until all the bits of the digital/analog converter have been ascertained successively.
The maximum conversion speed of the A/D converter 1 shown in FIG. 4 is determined by virtue of the n-bit A/D converter needing to make n decisions. In such A/D converters, the conversion rate is dependent primarily on the speed of the comparator 3. The speed of the comparator 3 is determined essentially by its recovery time after the linear input stage has been overdriven and secondly by the minimum switching time of the comparator 3 at a low drive level. Since the data bits of the digitally converted value are ascertained successively from the analog input signal, the conversion rate is much lower in comparison with a parallel converter or a cascade converter. A speed increase or an increase in the conversion rate for successive approximation analog/digital converters is therefore particularly desirable.
To increase the converter speed, A/D converters using a conversion algorithm with redundancy or with redundant code are therefore being used to an increasing extent. These A/D converters, which are subsequently also called redundant A/D converters for short, involve each conversion step permitting a greater or lesser error. FIG. 5 shows a redundant A/D converter of this kind, described in German patent DE 101 39 488 C1, for example. In this case, the redundant A/D converter 100 has a capacitive network 110 with a large number of individual reference capacitances 120. The individual reference capacitances 110 in this arrangement have a respective prescribed weighting such that the capacitive network 110 is thereby encoded with a redundant code. Either an analog input voltage UE or a reference voltage UREF for producing a comparison voltage can be applied to these reference capacitances 120 via respective controllable switches 130. The reference capacitances 120 together with the controllable switches 130 have the function of a D/A converter. The A/D converter 100 also has a separate comparator 140 whose inputs 150 are used to inject firstly the input voltage UE and secondly the comparison voltage produced from the reference voltage UREF, these being compared in the comparator 140. The comparator 140 can also be bridged by means of controllable switches 160 in order to sample and store the input voltage UE at the start of a conversion. The comparator 140 forwards the result from the comparison to an SAR register 170 which, on the basis of the instantaneous comparison result, actuates and selects the reference capacitances 120 in the capacitive network 110 for the subsequent comparison such that a gradual approximation, that is to say a successive approximation, to the actual input voltage UE is achieved. The comparison and gradual approximation are carried out down to the least significant bit (LSB). At the end of a conversion cycle of this kind, the SAR register 170 outputs the ascertained digital value UD, which is thus encoded with the redundant code from the capacitive network 110, to an adder 18. The adder 180 uses addition to correct the ascertained redundant code from the digital signal UD using the values stored in a memory 190 for the reference capacitances 120 and outputs the digital, for example binary encoded, output signal UD′ obtained in this way.
Nevertheless, the conversion speed and hence the conversion time for converting an analog input value into a digital output value cannot be shortened arbitrarily in the case of a successive approximation A/D converter. The reason for this, inter alia, is that the comparator can make only a single decision per conversion cycle.
Another aspect is the power loss in an A/D converter: if one considers the power loss in a successive approximation A/D converter, one finds that the majority of the power loss is consumed in its input driver (approximately 80% of the power loss), which thus needs to load the capacitances in the capacitive network, while the smaller component of the power loss is produced in the actual comparator in the A/D converter (approximately 20% of the power loss). The reason for this is that an A/D converter's input driver needs to operate as linearly as possible, whereas linearity plays a minor role in the actual comparator. Added to this is the fact that in a successive approximation A/D converter the influence of parasitic capacitances is very much greater at the input than is the case on the comparator. The result of this is that the input driver needs to drive very many more parasitic capacitances than the actual comparator.
In summary, it can therefore be stated that a successive approximation A/D converter has a relatively low conversion speed in comparison with other A/D converters. In addition, its power loss is also relatively high on account of the influence of the input drivers. A similarly disadvantageous characteristic is the need for the input driver to be given relatively large proportions on account of the great influence of parasitic capacitances on the input side.
To eliminate these drawbacks, it would admittedly be possible to use a cascade converter, which provides comparatively faster analog/digital conversion and also has a lower power loss on account of the larger number of comparators. However, a cascade converter has an unfavorable characteristic, particularly when using a multistage cascade converter and an associated large number of input capacitances, since the noise requirements in the case of a cascade converter require a very high level of capacity to be provided for every single input capacitance, and this complexity can increase the associated complexity exorbitantly, particularly with a large number of input capacitances.